Communities:
FPGA
| # | Tweet | Community | Topic | Views ▼ | Ratio | Engagement | Posted |
|---|---|---|---|---|---|---|---|
| 1 | [image] We have talked a lot about AI in SW, FPGA etc recently, one thing I had not explained is how I am using AI in my RTL developments. So this week I am explaining how.
It is just another level of abstraction which means, more than ever you need to know what your doing. | FPGA | — | 16.9K | 0.8x | 159 | Apr 1 |
| 2 | [text] How to develop IIR filters in FPGA. | FPGA | — | 15.9K | 0.7x | 162 | Apr 8 |
| 3 | [image] Like many FPGA Engineers, I have been experimenting with AI in our flow. One thing I have been thinking about is code quality, and how we can check what is generated by the AI model of choice.
Static RTL analysis should work well for this.
I did a experiment with the Claude, | FPGA | — | 15.3K | 0.7x | 176 | Mar 26 |
| 4 | [image] Fridays are for demos! What demos I am hoping to be able create with the newly arrived updated S7 Development board. This one has the S7-50 device and the RPI Pico. I also received new Pmods for testing Ethernet and HMDI Tx and Rx. | FPGA | — | 14.7K | 0.7x | 216 | Feb 27 |
| 5 | [image] The last few weeks have been exciting, we have been working on what we call the explorer board.
Cutting edge FPGA and interfacing.
Would love thoughts and feedback on this! | FPGA | — | 13.3K | 0.6x | 106 | Mar 24 |
| 6 | [image] Ethernet it working as well, RMII interface, and RTL IP core which will provide UDP support. | FPGA | — | 11.5K | 0.6x | 151 | Mar 1 |