FPGA

[image] We have talked a lot about AI in SW, FPGA etc recently, one thing I had not explained is how I am using AI in my RTL developments. So this week I am explaining how. It is just another level of abstraction which means, more than ever you need to know what your doing.

[text] How to develop IIR filters in FPGA.

[image] Like many FPGA Engineers, I have been experimenting with AI in our flow. One thing I have been thinking about is code quality, and how we can check what is generated by the AI model of choice. Static RTL analysis should work well for this. I did a experiment with the Claude,

[image] Fridays are for demos! What demos I am hoping to be able create with the newly arrived updated S7 Development board. This one has the S7-50 device and the RPI Pico. I also received new Pmods for testing Ethernet and HMDI Tx and Rx.

[image] The last few weeks have been exciting, we have been working on what we call the explorer board. Cutting edge FPGA and interfacing. Would love thoughts and feedback on this!

[image] Ethernet it working as well, RMII interface, and RTL IP core which will provide UDP support.